工作經驗 有相關經驗 年資:60月以上,學歷 碩士
★ ARM series CPU integration
★ System bus architecture design and implementation
★ Outstanding problem analysis and debugging skills
★ Experienced in Verilog RTL language
★ Experienced in digital IC design front-end flow
★ Experienced in CAD tool usage such as simulation tool, linting tool, synthesis tool, member compiler